A GitHub project called openTPU has achieved a notable milestone in AI-driven hardware design: an FPGA accelerator developed entirely by AI agents is now shipping and running real language models including Qwen3 and LFM2.5 on consumer hardware.
The project, developed by independent researcher FeSens, presents what it describes as the first fully AI-developed inference accelerator stack. The design includes register-transfer level (RTL) implementation, an instruction set architecture, compiler, simulator, and host tools—all generated through AI agent workflows.
The accelerator targets a Xilinx Kintex-7 FPGA mounted on an Inspur PCIe card, delivering hardware that AI agents helped design to run the very models used in its creation. The project frames this as a proof-of-concept addressing two fundamental questions: how far can AI agents progress in hardware design, and can they build the chips that execute their own inference workloads?
The full-stack implementation covers everything from matrix multiplication operations through accelerator instructions, explicit memory scheduling, and quantized execution support for documented language models. The design achieves approximately 0.56 tokens per second on Qwen2.5-0.5B—a 140-times speedup over prior FPGA implementations for language models.
Beyond the technical achievement, openTPU serves as an educational resource for understanding how compiler-to-RTL interactions work, prototyping FPGA inference flows, and experimenting with quantized model execution. The project is available under open-source licensing, inviting further development from the research community.
The work represents a closing loop in the AI hardware co-design space, where the tools used to develop and optimize language models are now themselves being designed with AI assistance. As model inference demands continue growing, such approaches may contribute to more specialized and efficient hardware deployments.